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document no. e0237e30 (ver. 3.0) date published august 2002 (k) japan url: http://www.elpida.com ? elpida memory, inc. 2002 preliminary data sheet 512m bits ddr sdram edd5104abta (128m words 4 bits) edd5108abta (64m words 8 bits) description the edd5104ab is a 512m bits double data rate (ddr) sdram organized as 33,554,432 words 4 bits 4 banks. the edd5108ab is a 512m bits ddr sdram organized as 16,777,216 words 8 bits 4 banks. read and write operations are performed at the cross points of the ck and the /ck. this high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. data strobe (dqs) both for read and write are available for high speed and reliable data bus design. by setting extended mode resistor, the on-chip delay locked loop (dll) can be set enable or disable. they are packaged in standard 66-pin plastic tsop (ii)10.16mm(400). features ? 2.5 v power supply: vddq = 2.5v 0.2v : vdd = 2.5v 0.2v ? data rate: 333mbps/266mbps (max.) ? double data rate architecture; two data transfers per clock cycle ? bi-directional, data strobe (dqs) is transmitted /received with data, to be used in capturing data at the receiver ? data inputs, outputs, and dm are synchronized with dqs ? 4 internal banks for concurrent operation ? dqs is edge aligned with data for reads; center aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? data mask (dm) for write data ? auto precharge option for each burst access ? 2.5 v (sstl_2 compatible) i/o ? programmable burst length (bl): 2, 4, 8 ? programmable /cas latency (cl): 2, 2.5 ? refresh cycles: 8192 refresh cycles/64ms ? 7.8 s maximum average periodic refresh interval ? 2 variations of refresh ? auto refresh ? self refresh pin configurations /xxx indicates active low signal. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc nc vddq nc nc vdd nc nc /we /cas /ras /cs nc ba0 ba1 a10(ap) a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc nc vssq dqs nc vref vss dm /ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 66-pin tsop(ii)10.16mm(400) (top view) vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd nc nc /we /cas /ras /cs nc ba0 ba1 a10(ap) a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm /ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss x 8 x 4 address input bank select address data-input/output input and output data strobe chip select row address strobe command column address strobe command write enable input mask clock input differential clock input clock enable input reference voltage power for internal circuit ground for internal circuit power for dq circuit ground for dq circuit no connection a0 to a12 ba0, ba1 dq0 to dq7 dqs /cs /ras /cas /we dm ck /ck cke vref vdd vss vddq vssq nc
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 2 ordering information part number mask version organization (words bits) internal banks data rate mbps (max.) jedec speed bin (cl-trcd-trp) package edd5104abta-6b EDD5104ABTA-7A edd5104abta-7b b 128m 4 4 333 266 266 ddr333b (2.5-3-3) ddr266a (2-3-3) ddr266b (2.5-3-3) edd5108abta-6b edd5108abta-7a edd5108abta-7b 64m 8 333 266 266 ddr333b (2.5-3-3) ddr266a (2-3-3) ddr266b (2.5-3-3) 66-pin plastic tsop (ii) 10.16mm(400) part number elpida memory density / bank 51: 512m / 4 banks bit organization 4: x4 8: x8 voltage, interface a: 2.5v, sstl_2 die rev. package ta: tsop (ii) speed 6b: ddr333b (2.5-3-3) 7a: ddr266a (2-3-3) 7b: ddr266b (2.5-3-3) product code d: ddr sdram type d: monolithic device e d d 51 04 a b ta - 6b
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 3 contents description.................................................................................................................... .................................1 features....................................................................................................................... ..................................1 pin configurations ............................................................................................................. ............................1 ordering information........................................................................................................... ...........................2 part number .................................................................................................................... ..............................2 electrical specifications...................................................................................................... ...........................4 block diagram .................................................................................................................. ...........................10 pin function................................................................................................................... ..............................11 command operation .............................................................................................................. .....................13 simplified state diagram ....................................................................................................... ......................21 operation of the ddr sdram ..................................................................................................... ...............22 timing waveforms............................................................................................................... ........................41 package drawing ................................................................................................................ ........................47 recommended soldering conditions ............................................................................................... ...........48
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 4 electrical specifications ? all voltages are referenced to vss (gnd). ? after power up, wait more than 200 s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol rating unit note voltage on any pin relative to vss vt ?1.0 to +3.6 v supply voltage relative to vss vdd ?1.0 to +3.6 v short circuit output current ios 50 ma power dissipation pd 1.0 w operating temperature ta 0 to +70 c storage temperature tstg ?55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (ta = 0 to 70 c) parameter symbol min typ max unit notes supply voltage vdd, vddq 2.3 2.5 2.7 v 1 vss, vssq 0 0 0 v input reference voltage vref 0.49 vddq 0.50 vddq 0.51 vddq v termination voltage vtt vref ? 0.04 vref vref + 0.04 v input high voltage vih (dc) vref + 0.15 ? vddq + 0.3 v 2 input low voltage vil (dc) ?0.3 ? vref ? 0.15 v 3 input voltage level, ck and /ck inputs vin (dc) ?0.3 ? vddq + 0.3 v 4 input differential cross point voltage, ck and /ck inputs vix (dc) 0.5 vddq ? 0.2v 0.5 vddq 0.5 vddq + 0.2v v input differential voltage, ck and /ck inputs vid (dc) 0.36 ? vddq + 0.6 v 5, 6 notes: 1. vddq must be lower than or equal to vdd. 2. vih is allowed to exceed vdd up to 3.6v for the period shorter than or equal to 5ns. 3. vil is allowed to outreach below vss down to ?1.0v for the period shorter than or equal to 5ns. 4. vin (dc) specifies the allowable dc execution of each differential input. 5. vid (dc) specifies the input differential voltage required for switching. 6. vih (ck) min assumed over vref + 0.18v, vil (ck) max assumed under vref ? 0.18v if measurement.
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 5 dc characteristics 1 (ta = 0 to +70 c, vdd, vddq = 2.5v 0.2v, vss, vssq = 0v) max. parameter symbol grade 4 8 unit test condition notes operating current (act-pre) idd0 -6b -7a, -7b 150 135 150 135 ma cke vih, trc = trc (min.) 1, 2, 9 operating current (act-read-pre) idd1 -6b -7a, -7b 170 155 180 160 ma cke vih, bl = 4, cl = 2.5, trc = trc (min.) 1, 2, 5 idle power down standby current idd2p 3 3 ma cke vil 4 floating idle standby current idd2f -6b -7a, -7b 40 35 40 35 ma cke vih, /cs vih, dq, dqs, dm = vref 4, 5 quiet idle standby current idd2q 25 25 ma cke vih, /cs vih, dq, dqs, dm = vref 4, 10 active power down standby current idd3p 20 20 ma cke vil 3 active standby current idd3n -6b -7a, -7b 70 60 70 60 ma cke vih, /cs vih tras = tras (max.) 3, 5, 6 operating current (burst read operation) idd4r -6b -7a, -7b 200 170 210 180 ma cke vih, bl = 2, cl = 2.5 1, 2, 5, 6 operating current (burst write operation) idd4w -6b -7a, -7b 200 170 210 180 ma cke vih, bl = 2, cl = 2.5 1, 2, 5, 6 auto refresh current idd5 -6b -7a, -7b 290 270 290 270 ma trfc = trfc (min.), input vil or vih self refresh current idd6 4 4 ma input vdd ? 0.2 v input 0.2 v operating current (4 banks interleaving) idd7a -6b -7a, -7b 420 360 430 370 ma bl = 4 5, 6, 7 notes: 1. these idd data are measured under condition that dq pins are not connected. 2. one bank operation. 3. one bank active. 4. all banks idle. 5. command/address transition once per one clock cycle. 6. dq, dm and dqs transition twice per one clock cycle. 7. 4 banks active. only one bank is running at trc = trc (min.) 8. the idd data on this table are measured with regard to tck = tck (min.) in general. 9. command/address transition once every two clock cycles. 10. command/address stable at vih or vil. dc characteristics 2 (ta = 0 to +70 c, vdd, vddq = 2.5v 0.2v, vss, vssq = 0v) parameter symbol min. max. unit test condition notes input leakage current il ?2 2 a vdd vin vss output leakage current ioz ?5 5 a vddq vout vss output high current ioh ?15.2 ? ma vout = 1.95v output low current iol 15.2 ? ma vout = 0.35v
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 6 pin capacitance (ta = +25c, vdd, vddq = 2.5v 0.2v) parameter symbol pins min. typ max. unit notes input capacitance ci1 ck, /ck 2.0 ? 3.0 pf 1 ci2 all other input pins 2.0 ? 3.0 pf 1 delta input capacitance cdi1 ck, /ck ? ? 0.25 pf 1 cdi2 all other input-only pins ? ? 0.5 pf 1 data input/output capacitance ci/o dq, dm, dqs 4.0 ? 5 pf 1, 2, delta input/output capacitance cdio dq, dm, dqs ? ? 0.5 pf 1 notes: 1. these parameters are measured on conditions: f = 100mhz, vout = vddq/2, ? vout = 0.2v, ta = +25 c. 2. dout circuits are disabled. ac characteristics (ta = 0 to +70 c, vdd, vddq = 2.5v 0.2v, vss, vssq = 0v) -6b -7a -7b parameter symbol min. max. min. max min. max. unit notes clock cycle time (cl = 2) tck 7.5 12 7.5 12 10 12 ns 10 (cl = 2.5) tck 6 12 7.5 12 7.5 12 ns ck high-level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck ck half period thp min (tch, tcl) ? min (tch, tcl) ? min (tch, tcl) ? tck dq output access time from ck, /ck tac ?0.7 0.7 ?0.75 0.75 ?0.75 0.75 ns 2, 11 dqs output access time from ck, /ck tdqsc k ?0.6 0.6 ?0.75 0.75 ?0.75 0.75 ns 2, 11 dqs to dq skew tdqsq ? 0.45 ? 0.5 ? 0.5 ns 3 dq/dqs output hold time from dqs tqh thp ? tqhs ? thp ? tqhs ? thp ? tqhs ? ns data hold skew factor tqhs ? 0.55 ? 0.75 ? 0.75 ns data-out high-impedance time from ck, /ck thz ?0.7 0.7 ?0.75 0.75 ?0.75 0.75 ns 5, 11 data-out low-impedance time from ck, /ck tlz ?0.7 0.7 ?0.75 0.75 ?0.75 0.75 ns 6, 11 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck dq and dm input setup time tds 0.45 ? 0.5 ? 0.5 ? ns 8 dq and dm input hold time tdh 0.45 ? 0.5 ? 0.5 ? ns 8 dq and dm input pulse width tdipw 1.75 ? 1.75 ? 1.75 ? ns 7 write preamble setup time twpre s 0 ? 0 ? 0 ? ns write preamble twpre 0.25 ? 0.25 ? 0.25 ? tck write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 9 write command to first dqs latching transition tdqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs falling edge to ck setup time tdss 0.2 ? 0.2 ? 0.2 ? tck dqs falling edge hold time from ck tdsh 0.2 ? 0.2 ? 0.2 ? tck dqs input high pulse width tdqsh 0.35 ? 0.35 ? 0.35 ? tck dqs input low pulse width tdqsl 0.35 0.35 ? 0.35 ? tck
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 7 -6b -7a -7b parameter symbol min. max. min. max min. max. unit notes address and control input setup time tis 0.75 ? 0.9 ? 0.9 ? address and control input hold time tih 0.75 ? 0.9 ? 0.9 ? ns 8 address and control input pulse width tipw 2.2 ? 2.2 ? 2.2 ? ns 7 mode register set command cycle time tmrd 2 ? 2 ? 2 ? tck active to precharge command period tras 42 120000 45 120000 45 120000 ns active to active/auto refresh command period trc 60 ? 67.5 ? 67.5 ? ns auto refresh to active/auto refresh command period trfc 72 ? 75 ? 75 ? ns active to read/write delay trcd 18 ? 20 ? 20 ? ns precharge to active command period trp 18 ? 20 ? 20 ? ns active to autoprecharge delay trap trcd min. ? trcd min. ? trcd min. ? ns active to active command period trrd 12 ? 15 ? 15 ? ns write recovery time twr 15 ? 15 ? 15 ? ns auto precharge write recovery and precharge time tdal (twr/tck)+ (trp/tck) (twr/tck)+ (trp/tck) ? (twr/tck)+ (trp/tck) ? tck 13 internal write to read command delay twtr 1 ? 1 ? 1 ? tck average periodic refresh interval tref ? 7.8 ? 7.8 ? 7.8 s notes: 1. on all ac measurements, we assume the test conditions shown in the next page. for timing parameter definitions, see ?timing waveforms? section. 2. this parameter defines the signal transition delay from the cross point of ck and /ck. the signal transition is defined to occur when the signal level crossing vtt. 3. the timing reference level is vtt. 4. output valid window is defined to be the period between two successive transition of data out or dqs (read) signals. the signal transition is defined to occur when the signal level crossing vtt. 5. thz is defined as dout transition delay from low-z to high-z at the end of read burst operation. the timing reference is cross point of ck and /ck. this parameter is not referred to a specific dout voltage level, but specify when the device output stops driving. 6. tlz is defined as dout transition delay from high-z to low-z at the beginning of read operation. this parameter is not referred to a specific dout voltage level, but specify when the device output begins driving. 7. input valid windows is defined to be the period between two successive transition of data input or dqs (write) signals. the signal transition is defined to occur when the signal level crossing vref. 8. the timing reference level is vref. 9. the transition from low-z to high-z is defined to occur when the device output stops driving. a specific reference voltage to judge this transition is not given. 10. tck (max.) is determined by the lock range of the dll. beyond this lock range, the dll operation is not assured. 11. tck = tck (min.) when these parameters are measured. otherwise, absolute minimum values of these values are 10% of tck. 12. vdd is assumed to be 2.5v 0.2v. vdd power supply variation per cycle expected to be less than 0.4v/400 cycle. 13. tdal = (twr/tck)+(trp/tck) for each of the terms above, if not already an integer, round to the next highest integer. example: for ?7a speed at cl = 2.5, tck = 7.5ns, twr = 15ns and trp= 20ns, tdal = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3) tdal = 5 clocks
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 8 test conditions parameter symbol value unit input reference voltage vref vddq/2 v termination voltage vtt vref v input high voltage vih (ac) vref + 0.31 v input low voltage vil (ac) vref ? 0.31 v input differential voltage, ck and /ck inputs vid (ac) 0.62 v input differential cross point voltage, ck and /ck inputs vix (ac) vref v input signal slew rate slew 1 v/ns vtt vref /ck ck vref vss slew = (vih (ac) ? vil (ac))/ ? t measurement point vih vil vdd vdd vss dq rt = 50 ? cl = 30pf vix ? t tcl tck tch vid input waveforms and output load
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 9 timing parameter measured in clock cycle number of clock cycle tck 6ns 7.5ns parameter symbol min. max. min. max. write to pre-charge command delay (same bank) twpd 4 + bl/2 3 + bl/2 read to pre-charge command delay (same bank) trpd bl/2 bl/2 write to read command delay (to input all data) twrd 2 + bl/2 2 + bl/2 burst stop command to write command delay (cl = 2) tbstw 2 2 (cl = 2.5) tbstw 3 3 burst stop command to dq high-z (cl = 2) tbstz 2 2 2 2 (cl = 2.5) tbstz 2.5 2.5 2.5 2.5 read command to write command delay (to output all data) (cl = 2) trwd 2 + bl/2 2 + bl/2 (cl = 2.5) trwd 3 + bl/2 3 + bl/2 pre-charge command to high-z (cl = 2) thzp 2 2 2 2 (cl = 2.5) thzp 2.5 2.5 2.5 2.5 write command to data in latency twcd 1 1 1 1 write recovery time twr 3 2 dm to data in latency tdmd 0 0 0 0 mode register set command cycle time tmrd 2 2 self refresh exit to non-read command tsnr 12 10 self refresh exit to read command tsrd 200 200 power down entry tpden 1 1 1 1 power down exit to command input tpdex 1 1
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 10 block diagram a0 to a12, ba0, ba1 /cs /ras /cas /we command decoder input & output buffer latch circuit data control circuit column decoder row decoder memory cell array bank 0 sense amp. bank 1 bank 2 bank 3 control logic column address buffer and burst counter row address buffer and refresh counter mode register clock generator dq ck /ck cke dqs dm dll ck, /ck
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 11 pin function ck, /ck (input pins) the ck and the /ck are the master clock inputs. all inputs except dm, dqs and dqs are referred to the cross point of the ck rising edge and the /ck falling edge. when a read operation, dqs and dqs are referred to the cross point of the ck and the /ck. when a write operation, dqs and dqs are referred to the cross point of the dqs and the vref level. dqs for write operation is referred to the cross point of the ck and the /ck. ck is the master clock input to this pin. the other input signals are referred at ck rising edge. /cs (input pin) when /cs is low, commands and data can be input. when /cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /ras, /cas, and /we (input pins) these pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. see "command operation". a0 toa12 (input pins) row address (ax0 to ax12) is determined by the a0 to the a12 level at the cross point of the ck rising edge and the /ck falling edge in a bank active command cycle. column address (see ?address pins table?) is loaded via the a0 to the a9, a11 and a12 at the cross point of the ck rising edge and the /ck falling edge in a read or a write command cycle. this column address becomes the starting address of a burst operation. [address pins table] address (a0 to a12) part number row address column address edd5104ab ax0 to ax12 ay0 to ay9, ay11, ay12 edd5108ab ax0 to ax12 ay0 to ay9, ay11, a10 (ap) (input pin) a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1/ba0 is precharged. if a10 = high when read or write command, auto-precharge function is enabled. while a10 = low, auto-precharge function is disabled. ba0 and ba1 (input pins) ba0, ba1 are bank select signals (ba). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 12 cke (input pin) this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low. cke controls power down and self-refresh. the power down and the self-refresh commands are entered when the cke is driven low and exited when it resumes to high. cke must be maintained high throughout read or write access. the cke level must be kept for 1 ck cycle at least, that is, if cke changes at the cross point of the ck rising edge and the /ck falling edge with proper setup time tis, by the next ck rising edge cke level must be kept with proper hold time tih. dm (input pin) dm is the reference signal of the data input mask function. dm is sampled at the cross point of dqs and vref. dq0 todq7 (input/output pins) data is input to and output from these pins (dq0 to dq3; edd5104ab, dq0 to dq7; edd5108ab). dqs (input and output pin): dqs provides the read data strobe (as output) and the write data strobe (as input). vdd, vss, vddq, vssq (power supply) vdd and vss are power supply pins for internal circuits. vddq and vssq are power supply pins for the output buffers.
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 13 command operation command truth table ddr sdram recognize the following commands specified by the /cs, /ras, /cas, /we and address pins. all other combinations than those in the table below are illegal. cke command symbol n ? 1 n /cs /ras /cas /we ba1 ba0 ap address ignore command desl h h h no operation nop h h l h h h burst stop in read command bst h h l h h l column address and read command read h h l h l h v v l v read with auto-precharge reada h h l h l h v v h v column address and write command writ h h l h l l v v l v write with auto-precharge writa h h l h l l v v h v row address strobe and bank active act h h l l h h v v v v precharge select bank pre h h l l h l v v l precharge all bank pall h h l l h l h refresh ref h h l l l h self h l l l l h mode register set mrs h h l l l l l l l v emrs h h l l l l l h l v remark: h: vih. l: vil. : vih or vil v: valid address input note: the cke level must be kept for 1 ck cycle at least. ignore command [desl] when /cs is high at the cross point of the ck rising edge and the vref level, every input are neglected and internal status is held. no operation [nop] as long as this command is input at the cross point of the ck rising edge and the vref level, address and data input are neglected and internal status is held. burst stop in read operation [bst] this command stops a burst read operation, which is not applicable for a burst write operation. column address strobe and read command [read] this command starts a read operation. the start address of the burst read is determined by the column address (see ?address pins table? in pin function) and the bank select address. after the completion of the read operation, the output buffer becomes high-z. read with auto-precharge [reada] this command starts a read operation. after completion of the read operation, precharge is automatically executed. column address strobe and write command [writ] this command starts a write operation. the start address of the burst write is determined by the column address (see ?address pins table? in pin function) and the bank select address. write with auto-precharge [writa] this command starts a write operation. after completion of the write operation, precharge is automatically executed.
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 14 row address strobe and bank activate [act] this command activates the bank that is selected by ba0, ba1 and determines the row address (ax0 to ax12). (see bank select signal table) precharge selected bank [pre] this command starts precharge operation for the bank selected by ba0, ba1. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil precharge all banks [pall] this command starts a precharge operation for all banks. refresh [ref/self] this command starts a refresh operation. there are two types of refresh operation, one is auto-refresh, and another is self-refresh. for details, refer to the cke truth table section. mode register set/extended mode register set [mrs/emrs] the ddr sdram has the two mode registers, the mode register and the extended mode register, to defines how it works. the both mode registers are set through the address pins (the a0 to the a12, ba0 to ba1) in the mode register set cycle. for details, refer to "mode register and extended mode register set". cke truth table cke current state command n ? 1 n /cs /ras /cas /we address notes idle auto-refresh command (ref) h h l l l h 2 idle self-refresh entry (self) h l l l l h 2 idle power down entry (pden) h l l h h h h l h self refresh self refresh exit (selfx) l h l h h h l h h power down power down exit (pdex) l h l h h h l h h remark: h: vih. l: vil. : vih or vil. notes: 1. all the banks must be in idle before executing this command. 2. the cke level must be kept for 1 ck cycle at least.
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 15 function truth table the following tables show the operations that are performed when each command is issued in each state of the ddr sdram. function truth table (1) current state /cs /ras /cas /we address command operation next state precharging* 1 h desl nop ldle l h h h nop nop ldle l h h l bst illegal* 11 ? l h l h ba, ca, a10 read/reada illegal* 11 ? l h l l ba, ca, a10 writ/writa illegal* 11 ? l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall nop ldle l l l illegal ? idle* 2 h desl nop ldle l h h h nop nop ldle l h h l bst illegal* 11 ? l h l h ba, ca, a10 read/reada illegal* 11 ? l h l l ba, ca, a10 writ/writa illegal* 11 ? l l h h ba, ra act activating active l l h l ba, a10 pre, pall nop ldle l l l h ref, self refresh/ self refresh* 12 ldle/ self refresh l l l l mode mrs mode register set* 12 ldle refresh (auto-refresh)* 3 h desl nop ldle l h h h nop nop ldle l h h l bst illegal ? l h l illegal ? l l illegal ?
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 16 function truth table (2) current state /cs /ras /cas /we address command operation next state activating* 4 h desl nop active l h h h nop nop active l h h l bst illegal* 11 ? l h l h ba, ca, a10 read/reada illegal* 11 ? l h l l ba, ca, a10 writ/writa illegal* 11 ? l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall illegal* 11 ? l l l illegal ? active* 5 h desl nop active l h h h nop nop active l h h l bst illegal active l h l h ba, ca, a10 read/reada starting read operation read/reada l h l l ba, ca, a10 writ/writa starting write operation write recovering/ precharging l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall pre-charge idle l l l illegal ? read* 6 h desl nop active l h h h nop nop active l h h l bst bst active l h l h ba, ca, a10 read/reada interrupting burst read operation to start new read active l h l l ba, ca, a10 writ/writa illegal* 13 ? l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall interrupting burst read operation to start pre-charge precharging l l l illegal ?
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 17 function truth table (3) current state /cs /ras /cas /we address command operation next state read with auto-pre- charge* 7 h desl nop precharging l h h h nop nop precharging l h h l bst illegal ? l h l h ba, ca, a10 read/reada illegal* 14 ? l h l l ba, ca, a10 writ/writa illegal* 14 ? l l h h ba, ra act illegal* 11, 14 ? l l h l ba, a10 pre, pall illegal* 11, 14 ? l l l illegal ? write* 8 h desl nop write recovering l h h h nop nop write recovering l h h l bst illegal ? l h l h ba, ca, a10 read/reada interrupting burst write operation to start read operation. read/reada l h l l ba, ca, a10 writ/writa interrupting burst write operation to start new write operation. write/writea l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre, pall interrupting write operation to start pre- charge. idle l l l illegal ? write recovering* 9 h desl nop active l h h h nop nop active l h h l bst illegal ? l h l h ba, ca, a10 read/reada starting read operation. read/reada l h l l ba, ca, a10 writ/writa starting new write operation. write/writea l l h h ba, ra act illegal* 11 ? l l h l ba, a10 pre/pall illegal* 11 ? l l l illegal ? write with auto- pre-charge* 10 h desl nop precharging l h h h nop nop precharging l h h l bst illegal ? l h l h ba, ca, a10 read/reada illegal* 14 ? l h l l ba, ca, a10 writ/writ a illegal* 14 ? l l h h ba, ra act illegal* 11, 14 ? l l h l ba, a10 pre, pall illegal* 11, 14 ? l l l illegal ? remark: h: vih. l: vil. : vih or vil
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 18 notes: 1. the ddr sdram is in "precharging" state for trp after precharge command is issued. 2. the ddr sdram reaches "idle" state trp after precharge command is issued. 3. the ddr sdram is in "refresh" state for trfc after auto-refresh command is issued. 4. the ddr sdram is in "activating" state for trcd after act command is issued. 5. the ddr sdram is in "active" state after "activating" is completed. 6. the ddr sdram is in "read" state until burst data have been output and dq output circuits are turned off. 7. the ddr sdram is in "read with auto-precharge" from reada command until burst data has been output and dq output circuits are turned off. 8. the ddr sdram is in "write" state from writ command to the last burst data are input. 9. the ddr sdram is in "write recovering" for twr after the last data are input. 10. the ddr sdram is in "write with auto-precharge" until twr after the last data has been input. 11. this command may be issued for other banks, depending on the state of the banks. 12. all banks must be in "idle". 13. before executing a write command to stop the preceding burst read operation, bst command must be issued. 14. edd5104abta and edd5108abta support the concurrent auto-precharge feature, a read with auto- precharge enabled,or a write with auto-precharge enabled, may be followed by any column command to other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply. (e.g. conflict between read data and write data must be avoided.) the minimum delay from a read or write command with auto precharge enabled, to a command to a different bank, is summarized below. from command to command (different bank, non- interrupting command) minimum delay (concurrent ap supported) units read w/ap read or read w/ap bl/2 tck write or write w/ap cl(rounded up)+ (bl/2) tck precharge or activate 1 tck write w/ap read or read w/ap 1 + (bl/2) + twtr tck write or write w/ap bl/2 tck precharge or activate 1 tck
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 19 command truth table for cke current state cke n ? 1 n /cs /ras /cas /we address operation notes self refresh h invalid, ck (n-1) would exit self refresh l h h self refresh recovery l h l h h self refresh recovery l h l h l illegal l h l l illegal l l maintain self refresh self refresh recovery h h h idle after trc h h l h h idle after trc h h l h l illegal h h l l illegal h l h illegal h l l h h illegal h l l h l illegal h l l l illegal power down h invalid, ck (n ? 1) would exit power down l h h exit power down idle l h l h h h l l maintain power down mode all banks idle h h h refer to operations in function truth table h h l h refer to operations in function truth table h h l l h refer to operations in function truth table h h l l l h cbr (auto) refresh h h l l l l opcode refer to operations in function truth table h l h refer to operations in function truth table h l l h refer to operations in function truth table h l l l h refer to operations in function truth table h l l l l h self refresh 1 h l l l l l opcode refer to operations in function truth table l power down 1 row active h refer to operations in function truth table l power down 1 remark: h: vih. l: vil. : vih or vil note: self refresh can be entered only from the all banks idle state. power down can be entered only from all banks idle or row active state.
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 20 auto-refresh command [ref] this command executes auto-refresh. the banks and the row addresses to be refreshed are internally determined by the internal refresh controller. the average refresh cycle is 7.8 s. the output buffer becomes high-z after auto- refresh start. precharge has been completed automatically after the auto-refresh. the act or mrs command can be issued trfc after the last auto-refresh command. self-refresh entry [self] this command starts self-refresh. the self-refresh operation continues as long as cke is held low. during the self- refresh operation, all row addresses are repeated refreshing by the internal refresh controller. a self-refresh is terminated by a self-refresh exit command. power down mode entry [pden] tpden (= 1 cycle) after the cycle when [pden] is issued. the ddr sdram enters into power-down mode. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. no internal refresh operation occurs during the power down mode. [pden] do not disable dll. self-refresh exit [selfx] this command is executed to exit from self-refresh mode. to issue non-read commands, tsnr has to be satisfied. ((tsnr =)10 cycles for tck = 7.5 ns or 12 cycles for tck = 6.0 ns after [selfx]) to issue read command, tsrd has to be satisfied to adjust dout timing by dll. (200 cycles after [selfx]) after the exit, input auto-refresh command within 7.8 s. power down exit [pdex] the ddr sdram can exit from power down mode tpdex (1 cycle min.) after the cycle when [pdex] is issued.
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 21 simplified state diagram precharge row active idle idle power down auto refresh self refresh mode register set active power down power on writea reada sr entry sr exit mrs refresh cke cke_ cke cke_ active write read bst write with ap read with ap power applied precharge ap read write with ap read with read with ap precharge precharge precharge *1 read read write write automatic transition after completion of command. transition resulting from command input. note: 1. after the auto-refresh operation, precharge operation is performed automatically and enter the idle state.
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 22 operation of the ddr sdram power-up sequence the following sequence is recommended for power-up. (1) apply power and attempt to maintain cke at an lvcmos low state (all other inputs may be undefined). apply vdd before or at the same time as vddq. apply vddq before or at the same time as vtt and vref. (2) start clock and maintain stable condition for a minimum of 200 s. (3) after the minimum 200 s of stable power and clock (ck, /ck), apply nop and take cke high. (4) issue precharge all command for the device. (5) issue emrs to enable dll. (6) issue a mode register set command (mrs) for "dll reset" with bit a8 set to high (an additional 200 cycles of clock input is required to lock the dll after every dll reset). (7) issue precharge all command for the device. (8) issue 2 or more auto-refresh commands. (9) issue a mode register set command to initialize device operation. command emrs pall mrs ref 2 cycles (min.) 2 cycles (min.) 200 cycles (min) 2 cycles (min.) 2 cycles (min.) t rp t rfc t rfc pall mrs ref ref any command dll enable dll reset /ck ck power-up sequence after cke goes high mode register and extended mode register set there are two mode registers, the mode register and the extended mode register so as to define the operating mode. parameters are set to both through the a0 to the a12 and ba0, ba1 pins by the mode register set command [mrs] or the extended mode register set command [emrs]. the mode register and the extended mode register are set by inputting signal via the a0 to the a12 and ba0, ba1 during mode register set cycles. ba0 and ba1 determine which one of the mode register or the extended mode register are set. prior to a read or a write operation, the mode register must be set. remind that no other parameters are shown in the table bellow are allowed to input to the registers. a2 a1 a0 burst length 001 2 010 4 011 8 bt=0 bt=1 2 4 8 a3 0 sequential 1 interleave burst type a6 a5 a4 cas latency 010 2 2.5 110 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 000 0 dr lmode bt bl a8 0no 1 yes dll reset a11 a10 a12 ba1 0 ba0 0 mrs mode register set [mrs] (ba0 = 0, ba1 = 0)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 23 a0 0 dll enable 1 dll disable dll control a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 00 0 0 00 0 0 0 0 dll 0 a11 a10 a12 ba1 0 ba0 1 emrs extended mode register set [emrs] (ba0 = 1, ba1 = 0) burst operation the burst type (bt) and the first three bits of the column address determine the order of a data out. a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequence 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequence starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequence starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 24 read/write operations bank active a read or a write operation begins with the bank active command [act]. the bank active command determines a bank address and a row address. for the bank and the row, a read or a write command can be issued trcd after the act is issued. read operation the burst length (bl), the /cas latency (cl) and the burst type (bt) of the mode register are referred when a read command is issued. the burst length (bl) determines the length of a sequential output data by the read command that can be set to 2, 4, or 8. the starting address of the burst read is defined by the column address, the bank select address which are loaded via the a0 to a12 and ba0, ba1 pins in the cycle when the read command is issued. the data output timing are characterized by cl (2 or 2.5) and tac. the read burst start cl ? tck + tac (ns) after the clock rising edge where the read command are latched. the ddr sdram output the data strobe through dqs simultaneously with data. trpre prior to the first rising edge of the data strobe, the dqs are driven low from vtt level. this low period of dqs is referred as read preamble. the burst data are output coincidentally at both the rising and falling edge of the data strobe. the dq pins become high-z in the next cycle after the burst read operation completed. trpst from the last falling edge of the data strobe, the dqs pins become high-z. this low period of dqs is referred as read postamble. out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 ck /ck address dqs dq bl = 2 bl = 4 bl = 8 command cl = 2 bl: burst length t1 t0 t2 t3 t4 t5 t6 t7 t8 trcd trpre trpst act nop nop nop read row column read operation (burst length)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 25 ck /ck dqs vtt vtt vtt vtt dq dqs dq cl = 2 cl = 2.5 command t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 out0 out1 out2 out3 out0 out1 out2 out3 trpst trpre trpst tac,tdqsck read nop trpre tac,tdqsck read operation (/cas latency) write operation the burst length (bl) and the burst type (bt) of the mode register are referred when a write command is issued. the burst length (bl) determines the length of a sequential data input by the write command that can be set to 2, 4, or 8. the latency from write command to data input is fixed to 1. the starting address of the burst read is defined by the column address, the bank select address which are loaded via the a0 to a12, ba0 to ba1 pins in the cycle when the write command is issued. dqs should be input as the strobe for the input-data and dm as well during burst operation. twpre prior to the first rising edge of the dqs should be set to low and twpst after the last falling edge of the data strobe can be set to high-z. the leading low period of dqs is referred as write preamble. the last low period of dqs is referred as write postamble. in1 in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 in6 in7 ck /ck address dqs dq bl = 2 bl = 4 bl = 8 command bl: burst length t1 t0 t2 t3 t3.5 t4 t5 t6 t7 t8 in0 act nop nop nop write twpre twpres row column trcd twpst write operation
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 26 burst stop burst stop command during burst read the burst stop (bst) command is used to stop data output during a burst read. the bst command stops the burst read and sets the output buffer to high-z. tbstz (= cl) cycles after a bst command issued, the dq pins become high-z. the bst command is not supported for the burst write operation. note that bank address is not referred when this command is executed. ck /ck dqs dq dqs dq cl = 2 cl = 2.5 command t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 out0 out1 out0 out1 cl: /cas latency read bst nop 2 cycles tbstz tbstz 2.5 cycles burst stop during a read operation
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 27 auto precharge read with auto-precharge the precharge is automatically performed after completing a read operation. the precharge starts trpd (bl/2) cycle after reada command input. trap specification for reada allows a read command with auto precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tras (min) specification. a column command to the other active bank can be issued the next cycle after the last data output. read with auto-precharge command does not limit row commands execution for other bank. refer to ?function truth table (3) and related notes (notes.*14)?. out0 out1 out2 out3 ck /ck dq command trp (min) trap (min) = trcd (min) act note: internal auto-precharge starts at the timing indicated by " ". nop 2 cycles (= bl/2) reada act dqs tac,tdqsck trpd read with auto-precharge write with auto-precharge the precharge is automatically performed after completing a burst write operation. the precharge operation is started (bl/ 2 + 3) cycles after writa command issued. a column command to the other banks can be issued the next cycle after the internal precharge command issued. write with auto-precharge command does not limit row commands execution for other bank. refer to ?function truth table (3) and related notes (notes.*14)?. in1 in2 in3 in4 ck /ck dq command dm tras (min) trcd (min) trp dqs act writa act bl/2 + 3 cycles note: internal auto-precharge starts at the timing indicated by " ". bl = 4 nop nop burst write (bl = 4)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 28 command intervals a read command to the consecutive read command interval destination row of the consecutive read command bank address row address state operation 1. same same active the consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. 2. same different ? precharge the bank to interrupt the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. see ?a read command to the consecutive precharge interval? section. 3. different any active the consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. idle precharge the bank without interrupting the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. out a0 out a1 out b0 out b1 out b2 out b3 ck /ck address ba dq dqs command t1 t0 t2 t3 t4 t5 t6 t7 t8 bank0 active cl = 2 bl = 4 bank0 nop act nop read row column a read column b column = a read column = b read column = a dout column = b dout read to read command interval (same row address in the same bank)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 29 out a0 out a1 out b0 out b1 out b2 out b3 ck /ck address ba dq dqs command t1 t0 t2 t3 t4 t5 t6 t7 t8 t9 bank0 active bank3 active bank0 read bank3 read bank0 dout cl = 2 bl = 4 nop act nop nop row0 act read row1 column a read column b column = a read column = b read bank3 dout read to read command interval (different bank)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 30 a write command to the consecutive write command interval destination row of the consecutive write command bank address row address state operation 1. same same active the consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. 2. same different ? precharge the bank to interrupt the preceding write operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. see ?a write command to the consecutive precharge interval? section. 3. different any active the consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. idle precharge the bank without interrupting the preceding write operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. ina0 ina1 inb0 inb1 inb2 inb3 ck /ck address ba dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bank0 active bl = 4 bank0 nop dqs act nop writ row column a writ column b column = a write column = b write write to write command interval (same row address in the same bank)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 31 ina0 ina1 inb0 inb1 inb2 inb3 ck /ck address ba dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 t9 bank0 active bank3 active bank0 write bank3 write bl = 4 bank0, 3 nop dqs act nop act writ row0 row1 column a writ column b write to write command interval (different bank)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 32 a read command to the consecutive write command interval with the bst command destination row of the consecutive write command bank address row address state operation 1. same same active issue the bst command. tbstw ( tbstz) after the bst command, the consecutive write command can be issued. 2. same different ? precharge the bank to interrupt the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. see ?a read command to the consecutive precharge interval? section. 3. different any active issue the bst command. tbstw ( tbstz) after the bst command, the consecutive write command can be issued. idle precharge the bank independently of the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. out0 out1 in0 in1 in2 in3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl = 2 dqs output input tbstw ( tbstz) high-z read writ bst nop nop tbstz (= cl) read to write command interval
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 33 a write command to the consecutive read command interval: to complete the burst operation destination row of the consecutive read command bank address row address state operation 1. same same active to complete the burst operation, the consecutive read command should be performed twrd (= bl/ 2 + 2) after the write command. 2. same different ? precharge the bank twrd after the preceding write command. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. see ?a read command to the consecutive precharge interval? section. 3. different any active to complete a burst operation, the consecutive read command should be performed twrd (= bl/ 2 + 2) after the write command. idle precharge the bank independently of the preceding write operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. in0 in1 in2 in3 out2 out0 out1 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 bl = 4 cl = 2 twrd (min) twtr* dqs input output bl/2 + 2 cycle writ nop nop read note: twtr is referenced from the first positive ck edge after the last desired data in pair twtr. write to read command interval
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 34 a write command to the consecutive read command interval: to interrupt the write operation destination row of the consecutive read command bank address row address state operation 1. same same active dm must be input 1 cycle prior to the read command input to prevent from being written invalid data. in case, the read command is input in the next cycle of the write command, dm is not necessary. 2. same different ? ?* 1 3. different any active dm must be input 1 cycle prior to the read command input to prevent from being written invalid data. in case, the read command is input in the next cycle of the write command, dm is not necessary. idle ?* 1 note: 1. precharge must be preceded to read command. therefore read command can not interrupt the write operation in this case. write to read command interval (same bank, same row address) in0 in1 in2 out0 out1 out2 out3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl= 2 dqs cl=2 data masked 1 cycle read nop writ high-z high-z [write to read delay = 1 clock cycle]
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 35 in0 in1 in2 in3 out0 out1 out2 out3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl= 2 dqs cl=2 data masked 2 cycle read nop nop writ high-z high-z [write to read delay = 2 clock cycle] in0 in1 in2 in3 out0 out1 out2 out3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl= 2 dqs cl=2 data masked 3 cycle read writ nop nop note: twtr is referenced from the first positive ck edge after the last desired data in pair twtr. twtr* [write to read delay = 3 clock cycle]
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 36 a read command to the consecutive precharge command interval (same bank): to output all data to complete a burst read operation and get a burst length of data, the consecutive precharge command must be issued trpd (= bl/ 2 cycles) after the read command is issued. out0 out1 out2 out3 ck /ck dq dqs command t1 t0 t2 t3 t4 t5 t6 t7 t8 trpd = bl/2 read nop nop nop pre/ pall read to precharge command interval (same bank): to output all data (cl = 2, bl = 4) out0 out1 out2 out3 clk /clk dq dqs command t1 t0 t2 t3 t4 t5 t6 t7 t8 trpd = bl/2 read nop nop nop pre/ pall read to precharge command interval (same bank): to output all data (cl = 2.5, bl = 4)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 37 read to precharge command interval (same bank): to stop output data a burst data output can be interrupted with a precharge command. all dq pins and dqs pins become high-z thzp (= cl) after the precharge command. out0 out1 ck /ck dq dqs command t1 t0 t2 t3 t4 t5 t6 t7 t8 thzp read nop nop high-z high-z pre/pall read to precharge command interval (same bank): to stop output data (cl = 2, bl = 2, 4, 8) out0 out1 ck /ck dq dqs command t1 t0 t2 t3 t4 t5 t6 t7 t8 high-z high-z thzp cl = 2.5 read nop nop pre/pall read to precharge command interval (same bank): to stop output data (cl = 2.5, bl = 2, 4, 8)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 38 a write command to the consecutive precharge command interval (same bank) the minimum interval twpd ((bl/2 + 3 for tck = 7.5 ns, bl/2 + 4 for tck = 6 ns) cycles) is necessary between the write command and the precharge command. in0 in1 in2 in3 ck /ck dq dm dqs command t1 t0 t2 t3 t4 t5 t6 t7 last data input twpd writ nop nop twr pre/pall write to precharge command interval (same bank) (bl = 4) precharge termination in write cycles during a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same bank. in order to write the last input data, twr (min) must be satisfied. when the precharge command is issued, the invalid data must be masked by dm. in2 in3 in0 in1 ck /ck dq dm dqs command t1 t0 t2 t3 t4 t5 t6 t7 data masked writ nop nop twr pre/pall precharge termination in write cycles (same bank) (bl = 4)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 39 bank active command interval destination row of the consecutive act command bank address row address state operation 1. same any active two successive act commands can be issued at trc interval. in between two successive act operations, precharge command should be executed. 2. different any active precharge the bank. trp after the precharge command, the consecutive act command can be issued. idle trrd after an act command, the next act command can be issued. ck /ck command ba trc address actv trrd bank0 active bank3 active bank0 precharge bank0 active pre act row: 0 nop nop nop act act row: 1 row: 0 bank active to bank active mode register set to bank-active command interval the interval between setting the mode register and executing a bank-active command must be no less than tmrd. ck /ck command address nop nop mrs act tmrd mode register set bank3 active code bs and row
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 40 dm control dm can mask input data. by setting dm to low, data can be written. when dm is set to high, the corresponding data is not written, and the previous data is held. the latency between dm input and enabling/disabling mask function is 0. mask mask dqs dq dm t1 t2 t3 t4 t5 t6 write mask latency = 0 dm control
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 41 timing waveforms command and addresses input timing definition ck /ck vref command (/ras, /cas, /we, /cs) address tis tis tih tih vref read timing definition /ck ck dqs dq (dout) tlz tac tqh tac trpre tdqsck tdqsck tdqsck tqh tqh tdqsq tdqsq thz tqh tck tch tcl tdqsck tdqsq tdqsq tdqsck tdqsck trpst tac tac tqh write timing definition /ck ck dqs dm vref vref vref dq (din) tds tdh tdqss twpre twpres tds tdh tdipw tdipw tdipw tck tdsh tdss tdss tdqsl tdqsh twpst
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 42 read cycle bank 0 active bank 0 read bank 0 precharge cl = 2 bl = 4 bank0 access = vih or vil bank 0 active bank 0 read bank 0 precharge tis tih tch tck tcl tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis trpre tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih /ras a10 address high-z high-z /cs cke ck /ck /cas /we ba dqs dq (output) dm vih trcd tras trp trc trpst
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 43 write cycle bank 0 active cl = 2 bl = 4 bank0 access = vih or vil bank 0 active bank 0 write bank 0 precharge tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih vih trcd tras trc trp twr /cs ck /ck cke /ras /cas /we ba a10 address dq (input) dm dqs (input) tck tch tcl tds tds tds tdh tdh tdh tdqsh tdqsl twpst tdqss
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 44 mode register set cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 /ck ck cke /cs /ras /cas /we ba address dm dq (output) b valid code code trp precharge if needed mode register set bank 3 active bank 3 read r: b c: b vih bank 3 precharge tmrd high-z high-z cl = 2 bl = 4 = vih or vil dqs read/write cycle r:a c:a c:b r:b c:b'' b ?? bank 0 active bank 3 active bank 0 read bank 3 read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cke /ras /cs dqs /cas /we address ck ba dq (output) dq (input) /ck bank 3 write twrd high-z vih trwd b read cycle cl = 2 bl = 4 =vih or vil dm a
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 45 auto refresh cycle precharge if needed auto refresh bank 0 active bank 0 read /ck ck cke /cs /cas /we ba address dm dq (output) dq (input) /ras cl = 2 bl = 4 = vih or vil vih trp a10=1 r: b c: b b high-z trfc dqs
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 46 self refresh cycle self refresh entry self refresh exit high-z /ck cke /cs /ras /cas /we ba address dm dq (output) dq (input) ck precharge if needed bank 0 active bank 0 read trp tsnr a10=1 r: b c: b dqs cl = 2.5 bl = 4 = vih or vil tis tih cke = low tsrd
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 47 package drawing 66-pin plastic tsop (ii) 10.16mm(400) 0.10 0.65 66 34 133 22.22 0.10 1.0 0.05 1.20 max 10.16 0 to 8 0.91 max. 0.09 to 0.20 0.17 to 0.32 0.10 0.60 0.15 0.80 nom 0.25 +0.08 ? 0.05 11.76 0.20 eca-ts2-0029-01 note: this dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. a pin#1 id s 0.13 msa b unit: mm b * 1 s
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 48 recommended soldering conditions please consult with our sales offices for soldering conditions of the edd51xxabta. type of surface mount device e d d 51x x a b t a: 66-pin p l as t i c t s o p (ii) 10. 1 6 mm( 4 00)
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 49 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
edd5104abta, edd5108abta preliminary data sheet e0237e30 (ver. 3.0) 50 m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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